1. Field of the Invention
The present invention relates generally to methods for forming semiconductor structures, and more particularly to methods for forming field effect transistors (FETs) and epi-substrates.
2. Description of the Related Art
With advances in electronic products, semiconductor technology has been applied widely in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emitting diodes (LEDs), laser diodes and other devices or chip sets, in order to achieve high-integration and high-speed requirements, dimensions of semiconductor integrated circuits have been reduced and various materials, such as copper and ultra low-k dielectrics, have been proposed and are being used along with techniques for overcoming manufacturing obstacles associated with these materials and requirements. In order to achieve high-speed performance, dimensions of transistors have been shrinking. Salicidation technology has been widely applied in manufacturing transistors in order to reduce resistances of transistor gates and source/drain (S/D) contacts.
FIG. 1 is a schematic cross-sectional view showing a traditional field effect transistor (FET).
Referring to FIG. 1A, a gate oxide layer 110 and a polysilicon gate 120 are sequentially formed over a substrate 100. Spacers 130 are formed on sidewalls of the gate oxide layer 110 and die polysilicon gate 120. Lightly doped drain (LDD) regions 150 and source/drain (S/D) regions 160 are formed within the substrate 100 and adjacent to the gate oxide layer 110. Salicide layers 140 are formed on the polysilicon gate 120 and the S/D regions 160. Due to the salicide layers 140, which include metallic constituents, resistances of the polysilicon gate 120 and the S/D regions 160 are desirably achieved.
As the channel dimension of transistors is reduced, the thickness of the gate oxide layer 110 is also reduced. The thin gate oxide layer 110, however, is vulnerable to a voltage applied to the polysilicon gate 120 and may be damaged by the voltage. In order to mitigate the breakthrough effect of the gate oxide layer 110, a high dielectric constant material layer such as nitride or oxynitride is used such that the thickness of the gate dielectric layer 110 can be increased to sustain the voltage applied the polysilicon gate 120.
Based on the foregoing, improved methods for forming FET structures are desired.